The present invention relates to system-on-a-chip (SoC) design, and more specifically, to an intra-run design decision process for circuit synthesis.
In SoC design, a register-transfer level (RTL) design is implemented in a physical design based on processes that include high-level synthesis, logic synthesis, and physical synthesis. As part of one or more of the synthesis processes, different synthesis scenarios may be tried by modifying synthesis parameters (e.g., switch settings). A given synthesis run typically includes several stages. Parameters are often enacted at different stages of a synthesis run. Thus, parallel scenarios are possible at certain stages to consider different parameters, and parallel processing may be used to implement parallel runs. While an exhaustive trial of every scenario (every combination of parameters) may result in the most efficient physical design, each synthesis run represents a drain on available computational resources and disk space.